1. Field of the Invention
This invention relates to the testing of logic systems for use in all types of digital computers, including both general purpose and scientific computers. More specifically, the invention relates to a method and apparatus for testing the sensitivity of logic systems to AC timing variations.
2. Description of the Prior Art
The testing of logic subsystems in a computer system is a well-developed art, and is important in achieving highly reliable computer systems. It is also an important diagnostic tool not only for trouble-shooting existing computer systems but for examining and understanding the operation of logic subsystems with a view toward improving the design thereof. It is often desirable to test different aspects of logic system operation. For example, U.S. Pat. No. 3,659,087 issued on Apr. 25, 1972 to Green et al, and assigned to the same assignee as the present application, describes a technique for testing the sensitivity of a device under test (DUT) to pulse width. U.S. Pat. No. 3,633,174 issued on Jan. 4, 1972 to Griffin tests the sensitivity of a core memory to read strobe timing. U.S. Pat. No. 3,814,920 issued on June 4, 1974 to Huelters tests a device for logic faults.
The advent of Level Sensitive Logic Systems (LSSD) in digital computers has provided a minimization of race conditions, hazards and AC timing dependencies. Functional logic units are made solely dependent on the occurrence of the signals from plural clock trains, and this is accomplished by using clocked DC latches for all internal storage circuitry. The plural clock trains are synchronous and independent, and the various sets of latch circuitry are coupled through combinational logic to other sets of latches that are controlled by other system clock trains. For a more complete description of level sensitive logic systems, reference is made to commonly assigned U.S. Pat. Nos. 3,783,254 issued Jan. 1, 1974 to Eichelberger, and 4,063,080 issued Dec. 13, 1977 to Eichelberger et al, and the reference cited therein.
The designers of computer logic have had complete flexibility in arranging the timing relationships between the plural clock trains. For performance advantages, the clock relationships may be highly overlapped, underlapped, or offset by large fractions of the system cycle. Each of these implementations creates special path timing relationships that must be satisfied. System timing programs have been developed to aid the computer designer in meeting system path length criteria, but the independence of the programs to hardware, and the flexibility of the design arrangements, have often led to unexpected system timing problems in bring-up, and significant complexity in educating the field service personnel in diagnostic methods.
The advance of large scale integration (LSI) has further complicated system timing problems. It has become impossible to test each circuit for AC parameters such as rise delay, fall delay, rise time, etc. It has also become impractical to test for AC parameters at the Field Replacement Unit (FRU) level, and the first exposure to verification of system timing integrity occurs at the complete system level. The difficulty of timing verification can be better understood by considering the components involved in a system CPU. A high performance system may average 500 circuits/gates per chip and may contain up to 100 chips per FRU. A central processing unit may contain up to nine separate FRU's, and the total number of gates per CPU can therefore exceed 400,000. The number of critical paths within the CPU will be in the tens of thousands. Even a fraction of a percent of path timing errors could significantly impact hardware development cycles, and degradation of circuit performance in the field could also have a significant adverse impact on customer operation.
With increases in the complexity of logic systems, testing techniques have also become more sophisticated. U.S. Pat. No. 4,298,980 issued Nov. 3, 1981 to Hajdu et al, U.S. Pat. No. 3,916,306 issued Oct. 28, 1975 to Patti, and U.S. Pat. No. 3,761,695 issued Sept. 25, 1973 to Eichelberger, all commonly assigned with the present application, teach various techniques for testing the integrity of logic systems, i.e. testing for logic faults. However, while these testing techniques may detect logic hardware faults, there is a need for a better technique for isolating timing problems.
With increases in performance and operating speeds of computer systems, timing relationships between system functions have become more intricate, and the solving of timing problems has taken a higher priority. U.S. Pat. No. 4,058,757 issued Nov. 15, 1977 to Meuhldorf et al teaches a technique for measuring the switching times for a DUT. U.S. Pat. No. 4,144,448 issued Mar. 13, 1979 to Pisciotta et al discloses a technique for monitoring a plurality of clock signals. Maiden et al, "PROGRAMMABLE DIGITAL DELAY TEST CIRCUIT", IBM Technical Disclosure Bulletin, Vol. 24, No. 2, July 1981, pages 1176-1177, disclose a circuit for testing the sensitivity of channel interfaces to timing delays.
The use of unique timing relationships between plural (or multiple) clocks has allowed the computer designer the advantage of utilizing all timing techniques to obtain the best system path performance. However, the number of timing problems in both system bring-up and in timing failures in the field environment dictate that provision must be made for eliminating the dependencies of the past. New logical organizations must be utilized in computing systems to take advantage of high performance design. Timing dependencies and sensitivities must be controlled within the multiple clock train design.
Of specific interest in complex and high speed logic systems is the propagation delay of signals through the system. U.S. Pat. No. 3,805,152 issued Apr. 16, 1974 to Ebersman et al discloses a testing technique in which the output of a DUT is made to oscillate, with the frequency of oscillation representing the propagation delay. U.S. Pat. No. 3,784,907 issued Jan. 8, 1974 to Eichelberger discloses a propagation delay testing technique wherein a primary system input is changed and, after a predetermined time corresponding to an acceptable propagation delay through the selected path, the output of the path is monitored to see if a corresponding change has occurred.
The above-cited U.S. Pat. No. 4,063,080 to Eichelberger et al discloses a technique for propagation delay testing wherein inputs are provided to a logic system and, at a predetermined time later corresponding to the expected operating speed of the system, the output is monitored to determine if a corresponding change has occurred.
Ames et al, "ACCURATE PROPORTIONAL VARIABLE STRESS TESTING HARDWARE LOGIC DESIGN USING SOFTWARE SIMULATION", IBM Technical Disclosure Bulletin, Vol. 20, No. 1, June 1977, pages 6-8, disclose a technique for the stress testing of hardware logic design. This technique simulates propagation delays in order to assist in the design of logic systems.
It would be desirable in high performance computer systems to time stress the system logic to determine the failure margins, or to trouble-shoot marginal or unstable errors. Such a stressing function would be useful in engineering bring-up, and in field engineering diagnostics and trouble-shooting.